1. Field of the Invention
The present invention relates to a complementary MOS (CMOS) integrated circuit, and particularly to a CMOS integrated circuit in which a high voltage CMOS circuit and a low voltage CMOS circuit are formed on a semiconducting substrate.
2. Description of the Related Art
A CMOS integrated circuit including a plurality of circuits (for example, a high voltage circuit and a low voltage circuit) operated by different power supply voltages has such a structure as shown, for example, in Japanese Patent Laid-open No. HEI 2-284462. In this structure, a semiconducting substrate employed is set at a reference potential; divided wells each having a conducting type different from that of the semiconducting substrate are provided within the same plane region; and CMOS transistors are respectively formed in the divided wells, to constitute respective circuits, thus separating the power supply voltages of the circuits from each other.
The related art CMOS integrated circuit having the above structure, however, is disadvantageous in that the potential of the above well can be set at either positive or negative with respect to the reference potential depending on the conducting type of the semiconducting substrate. This makes it impossible to provide the circuit processing signals with both positive and negative polarities relative to the reference potential.
For this reason, in a system requiring a low voltage logic circuit and a circuit for outputting signals with both positive and negative polarities (for example, a CCD camera system or digital communication interface), the reference potentials are separately set on different chips, thereby causing a problem in making it difficult to achieve miniaturization by use of only one chip.